1. Field of the Invention
The present invention relates to a method for producing a multilayer printed or wiring circuit board, and more particularly pertains to a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement.
As the complexity of printed wiring boards increases, the need to increase the wiring density on each inner layer becomes more critical. Many complex PWB""s currently have wiring grids of 1.0 mm (40 mil). Future applications will drive the need to extend that wiring grid to 0.50 mm or less. This drives the need for smaller line widths and line spacings, as well as smaller wiring vias on the inner layers and external wiring surfaces circuit board as the wiring grid (pitch) decreases. Consequently, smaller via holes must be drilled throughout the length of the PWB, thereby presenting the challenge of very high aspect ratios (PWB thickness divided by via diameter) and the required processing to form such vias. The vias also consume valuable areas or so called real estate on the inner layers of the PWB""s which otherwise could be used for wiring density at more relaxed ground rules.
A PWB manufactured with a hierarchical design, could employ the use of innerlayers at varying wiring pitches which, when stacked together, produce the required wiring grid. In addition, if wiring vias are only extended through the length of the board for which an electrical connection for that wiring net is needed, the real estate normally consumed by the vias extending throughout the length of the PWB is now opened and available for circuit traces.
The concept for utilizing hierarchical electrical connections for multilayer printed wiring board structures which include substrates comprised of a dielectric material, such as an organic laminate, is known in the technology in that various electrically conductive elements are inserted into the interconnecting via or holes formed in the respective layers of the laminate, so as to enable the formation of electrical connections with the components intermediate some or all of the various layers, as may be required.
The manufacture and employment of multilayer printed wiring boards which include pluralities of conductive wiring layers intermediate dielectric layers conducive to forming a laminated structure is well known in the technology and in industry. In particular, the formation of lands for connection on the wiring layers and the forming of through holes or vias which extend through substantially one layer, or some or all of the layers of the printed wiring board dielectric material layers, and the coating of the vias with electrically conductive material so as to produce interlayer connections is also widely known.
In order to provide for the interconnection of the electrical components located on the surfaces of opposite sides of a layer, and/or the surfaces of additional layers of a multilayer printed wiring board, it is imperative that appropriate alignment be effected among the various holes or vias extending through respective superimposed layers of the laminate forming the printed wiring board, and to thereby be able to provide for appropriate interlayer electrical interconnections in an assured operative manner upon the filling of the vias or holes with an electrically conductive material, preferably such as a conductive paste.
2. Discussion of the Prior Art
Mizumoto et al U.S. Pat. No. 5,956,843, which is commonly assigned to the assignee of the present application, pertains to a multilayer printed wiring board and method of making thereof, in which a substrate constituted of a plurality of dielectric layers having electrically connecting components formed on the surfaces thereof so as to be either arranged externally or internally intermediate adjacent layers, and which are provided with vertically aligned through-holes or vias communicating between adjacent layers. Each of the holes may be equipped with electrically conductive plated layers or similar structures covering the surfaces of the holes or vias, and a conductive or non-conductive material, such as in the form of a paste, may be filled into each plated hole. Although the foregoing method of production and resultant structure set forth in this publication is generally satisfactory, the present invention improves thereon by essentially reducing manufacturing costs for such laminated printed wiring board structures incorporating multilayer arrangements with electrical interconnections, which in essence will permit the obtaining of higher processing yields under optimal economic manufacturing conditions. Higher yields will result from processing the individual layers within the capabilities and physical limitations. Also, because each layer can be processed in parallel, the individual layers could be fully tested prior to being laminated into a large multilayer board.
Yasumoto et al U.S. Pat. No. 4,612,083 discloses a process of fabricating three-dimensional semiconductor devices in which various laminated layers of a multilayer structure facilitate the formation of various electrical conductive interconnections in each of the respective layers, which are superimposed and laminated to each other. This entails a relatively complex manufacturing procedure, which although providing for appropriate electrical interconnects intermediate the various layers of the multilayer semiconductor device, requires extensive processing which appreciably increases the cost of manufacture.
Hxc3xcbner U.S. Pat. No. 5,902,118 discloses a method of producing a three-dimensional circuit arrangement wherein various layers of a semiconductor device are interconnected through the utilization of metallic components arranged in communication with operatively aligned drilled holes formed in the respective layers. This construction is complex and, resultingly, difficult to align during manufacture and assembly, so as to be conducive to extensive manufacturing costs in forming the multilayer or stacked electric circuit arrangement.
IBM Technical Disclosure Bulletin, Volume 33, No. 7 December 1990, entitled xe2x80x9cAutomatic Method For Registration and Stacking of Laminatesxe2x80x9d sets forth a method for automatically registering stacking thin laminates which are utilized in printed circuit board manufacturing. Again, although this provides for a generally satisfactory method of registering and stacking layers of a thin laminate forming a semiconductor structure, the processing apparatus is extremely complex in requiring the utilization of expensive robotics in order to provide for accurately aligned positioning of the various electric components, interconnects and layers.
IBM Technical Disclosure Bulletin, Volume 27, No. 5 October 1984, entitled xe2x80x9cMultilayer Subsurface Circuit Board Constructionsxe2x80x9d discloses the superposition of layers of a multilayer printed circuit board or wiring board, wherein metallic electrically conductive pins are inserted through aligned holes or vias previously formed in the layers, and wherein the holes are then at least partly filled with a conductive paste so as to provide for the interconnections of the electrical components arranged on internal and external layers of the laminated substrate forming the printed or wiring circuit board.
In essence, the present invention improves upon the prior art by providing a method and structure for creating z-axis interconnections in a high density wiring structure of a multilayer printed or wiring circuit board which will considerably increase the number of inputs and outputs (I/O) feasible in comparison with those of a standard wiring board design.
Basically, the invention enables an improved and simplified processing in the manufacture of such laminated multilayer printed wiring boards (PWBs) with higher I/O yields, in that each respective layer is individually processed at optimum conditions for a particular thickness for each such layer. In that instance, each layer has the required hole or arrays of holes or vias formed therein. The respective vias in each of these layers are filled to facilitate electrical interconnections with regard to components or wiring arranged on opposite sides of the layers or with components and wiring on an adjacent layer or surface upon lamination therewith so as optimize the manufacturing processes in a highly economical and efficient manner. The vias in the structure could also conceivably be filled during the lamination process by using a conductive material which is coated on a carrier that is pushed into the holes either selectively with a mask or non-selectively.
In particular, the invention facilitates the thickness of each layer to be governed by the aspect ratio drilling which is required, and enables the thickness of the layers, which may be constituted of either simple signal layers or multilayer panels, to be tailored to the drilling or other hole or via producing process which is optional for the diameter and panel thickness of the printed wiring board.
The present invention solves manufacturing and cost problems encountered in the industry, the latter of which includes additional thin layers being imparted to a printed wiring board, and keeps down the layer count and thickness in comparison with the state-of-the-art while obtaining a higher I/O yield. This is desirable, inasmuch as when the thickness of the printed wiring board is increased, it becomes increasingly difficult to effect a high aspect ratio processing for z-axis or multilayer interconnections, in effect, plated through-holes (PTHs), as well as plated copper surface thicknesses for circuitization. The present invention is not subject to these particular limitations, inasmuch as the process of producing the holes in each layer is implemented in thinner single layers prior to lamination of the individual layers of the printed wiring board.
Moreover, inasmuch as each of the holes or vias provided in each layer for forming the essentially multi-surfaced electrical interconnections is filled with a conductive paste, practically no or extremely little plating is required for the holes in order to produce the through-extending electrical connections, thus enabling any external circuitization to be as fine or dense as may be required by particular physical applications and customer needs. This, in particular, significantly reduces production time, in view of the potential elimination in the need for hole or via plating.
Accordingly, it is an object of the present invention to provide a novel and simplified method of producing a multilayer printed wiring board structure with z-axis interconnections.
Another object of the present invention is to provide a method of forming a structure for a laminated multilayer printed wiring board having circuitized surfaces and which are electrically interconnected by a plurality of aligned holes or vias which are formed pass through one or more of adjoiningly superimposed laminated layers of the printed wiring boards, and which holes are each filled with an electrically conductive paste which essentially forms the required intersurface and interlayer electrical connections.
Yet another object of the present invention is to provide a structure consisting of a laminated multilayer printed wiring board having interlayer electrical interconnects affected through vias which are filled with a conductive paste, and wherein the laminates form the necessary structure for a desired density in the number of electrical inputs and outputs.
Still another object of the present invention is to provide a structure consisting of a laminated multilayer printed wiring board having interlayer electrical interconnects effected through vias which are filled with a nonconductive paste, and wherein the vias in each of the innerlayers is overplated with another layer of metallization, such that a pad is formed upon which a conductive adhesive is dispensed which, after joining, forms the necessary structure for a desired density in the number of electrical inputs and outputs.
It is to be understood that the present invention offers the flexibility of creating many different interlayer connections and resultant structures that will become readily apparent to those skilled in the art.